TCA9548A_15 Datasheet, PDF (16/35 Pages) Texas Instruments – Low-Voltage 8-Channel I2C Switch With Reset

TCA9548A
SCPS207E – MAY 2012 – REVISED OCTOBER 2015
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8.5.3.2 Reads
Reading from a slave is very similar to writing, but the master will send a START condition, followed by the slave
address with the R/W bit set to 1 (signifying a read). The slave will acknowledge the read request, and the
master will release the SDA bus but will continue supplying the clock to the slave. During this part of the
transaction, the master will become the master-receiver, and the slave will become the slave-transmitter.
The master will continue to send out the clock pulses, but will release the SDA line so that the slave can transmit
data. At the end of every byte of data, the master will send an ACK to the slave, letting the slave know that it is
ready for more data. Once the master has received the number of bytes it is expecting, it will send a NACK,
signaling to the slave to halt communications and release the bus. The master will follow this up with a STOP
condition.
Figure 11 shows an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Device (Slave) Address (7 bits)
Control Register (8 bits)
S 1 1 1 0 A2 A1 A0 1 A B7 B6 B5 B4 B3 B2 B1 B0 NA P
START
R/W=1 ACK
Figure 11. Read from Control Register
NACK STOP
8.5.4 Control Register
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the TCA9548A (see Figure 12). This register can be written and read via the I²C
bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel.
Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I²C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are
received by the TCA9548A, it saves the last byte received.
Channel Selection Bits (Read/Write)
B7 B6 B5 B4 B3 B2 B1 B0
16
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Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Figure 12. Control Register
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