LP3950 Datasheet, PDF (6/38 Pages) National Semiconductor (TI) – Color LED Driver with Audio Synchronizer

LP3950
SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013
Block Diagram
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LDO
2.8V
C_VDD1
100 nF
V_REF
C_VREF
100 nF
RT
SINGLE ENDED
AUDIO SIGNAL
10 nF
RT
82k
ASE
10 nF
10 nF
DIFFERENTIAL
AUDIO SIGNAL
AD1
AD2
GNDA
C_VDD2
100 nF
V_DD1
OSC
V_REF
C_VDDA
100 nF
V_DD2
THSD
LP3950
BATTERY
V_DDA
C_IN
10 PF
SW
I_MAX = 300 mA
V_OUT = 4.1V TO 5.3V
L₁
4.7 PH
D1
FB
GND_BOOST
C_OUT
10 PF
EN
BOOST
ADC
AGC
FREQ
AMPL
PWM
SPI
RGB PATTERN
I²C
CTRL
GENERATOR
LEVEL SHIFTER
R1 ^RR1
R_G1
G1
R_B1
B1
R_R2
R2
R_G2
G2
B2 ^RB2
GND_RGB
MICROCONTROLLER
C_VDDIO
100 nF
Figure 2. LP3950 Block Diagram
Modes of Operation
RESET: In the RESET mode all the internal registers are reset to the default values. RESET is entered always if
input NRST is LOW or internal Power On Reset is active.
STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and RESET is not active. This is
the low power consumption mode, when all the circuit functions are disabled. Registers can be written in
this mode and the control bits are effective immediately after start up.
STARTUP: INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (V_REF, oscillator, etc.).
To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine.
Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal
shutdown event is present.
BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the
boost output is raised in PFM mode during the 10 ms delay generated by the state-machine. All RGB
outputs are off during the 10 ms delay to ensure smooth startup. The Boost startup is entered from
Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written
HIGH.
NORMAL: During the NORMAL mode the user controls the chip using the control registers. Registers can be
written in any sequence and any number of bits can be altered in a register within one write cycle . If the
default mode is selected, default control register values are used.
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