LP3950 Datasheet, PDF (11/38 Pages) National Semiconductor (TI) – Color LED Driver with Audio Synchronizer

LP3950
www.ti.com
SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013
I²C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA
signal transition from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transition
from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP bits. The I²C bus is
considered to be busy after START condition and free after STOP condition. During data transmission, the I²C
master can generate repeated START conditions. First START and repeated START conditions are equivalent,
function-wise.
SDA
SCL
S
START condition
P
STOP condition
Figure 7. Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3950 address is 50'h or 51'h. The selection of the address is
done by connecting SI pin to V_DDIO (51 hex) or GND (50 hex). For the eighth bit, a “0” indicates a WRITE and a
“1” indicates a READ. The second byte selects the register to which the data will be written. The third byte
contains data to write to the selected register.
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
1
1
0
1
1
0
I²C SLAVE address (chip address)
Figure 8. I²C Chip Address
ack from slave
ack from slave
ack from slave
start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb
ack stop
SCL
SDA
start
Id = 36h
w ack
addr = 02h
ack
DGGUHVV K¶02 data
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address, 50'h or 51'h for LP3950.
Figure 9. I²C Write Cycle
ack stop
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