LP3950 Datasheet, PDF (10/38 Pages) National Semiconductor (TI) – Color LED Driver with Audio Synchronizer

LP3950
SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013
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SS
2
1
5
4
3
12
SCK
SI
SO
7
6
MSB IN
BIT 14
Address
BIT 9
BIT 8
BIT 7
8
10
MSB OUT
R/W
BIT 1 LSB IN
BIT 1
11
9
LSB OUT
Data
Figure 5. SPI Timing Diagram
Table 1. SPI Timing Parameters⁽¹⁾
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
Cycle Time
Enable Lead Time
Enable Lag Time
Clock Low Time
Clock High Time
Data Setup Time
Data Hold Time
Data Access Time
Output Disable Time
Output Data Valid
Output Data Hold Time
SS Inactive Time
Parameter
Limit
Min
Max
80
40
40
40
40
0
20
27
27
37
0
15
(1) Data guaranteed by design.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I²C Compatible Interface
I²C SIGNALS
In I²C compatible mode, the LP3950 pin SCL is used for the I²C clock and the SDA pin is used for the I²C data.
Both these signals need a pull-up resistor according to I²C specification. The values of the pull-up resistors are
determined by the capacitance of the bus (typ. 1.8k). Signal timing specifications are shown in Table 2. Unused
pin SO can be left unconnected and pin SI must be connected to V_DDIO or GND (address selector). Maximum bit
rate is 400 kbit/s (V_DDIO 1.80V to V_DD1,2V). I²C compatible interface can be used down to 1.65 V_DDIO with
maximum bit rate of 200 kbit/s.
I²C DATA VALIDITY
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state
of the data line can only be changed when CLK is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 6. I²C Signals: Data Validity
10
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