LM3560 Datasheet, PDF (6/42 Pages) Texas Instruments – LM3560 Synchronous Boost Flash Driver w/ Dual 1A High-Side Current Sources (2A Total Flash Current)

Symbol
t_HD;DAT
t_SU;DAT
t_SU;STO
t_VD;DAT
t_VD;ACK
t_BUF
Parameter
Data Hold Time
Data Setup Time
Set-up Time for Stop
Condition
Data Valid Time
Data Valid
Acknowledge Time
Bus Free Time Between
a Start and a Stop
Condition
Conditions
Min
Typ
Max
Units
0
ns
100
ns
600
ns
900
ns
900
ns
1.3
µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see
the Electrical Characteristics table.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J=+150°C (typ.) and disengages at
T_J=+135°C (typ.). Thermal shutdown is guaranteed by design.
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1112: Micro SMD Wafer Level chip Scale
Package (AN-1112)
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = +125°C), the maximum power
dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θ_JA), as given by the
following equation: T_A-MAX = T_J-MAX-OP – (θ_JA × P_D-MAX).
Note 6: Junction-to-ambient thermal resistance (θ_JA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the
JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane
on the board is 50 mm x 50 mm. Thickness of copper layers are 36 µm/18 µm/18 µm/36 µm (1.5 oz/1oz/1oz/1.5 oz). Ambient temperature in simulation is 22°C,
still air. Power dissipation is 1W.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical (Typ) numbers are not guaranteed, but do represent the most likely
norm. Unless otherwise specified, conditions for typical specifications are: V_IN = 3.6V and T_A = +25°C.
Note 8: The typical curve for Current Limit is measured in closed loop using the typical application circuit by increasing I_OUT until the peak inductor current stops
increasing. The value given in the Electrical Table is measured open loop and is found by forcing current into SW until the current limit comparator threshold is
reached. Closed loop data appears higher due to the delay between the comparator trip point and the NFET turning off. This delay allows the closed loop inductor
current to ramp higher after the trip point by approximately 20ns × V_IN/L
Note 9: The typical curve for Over-Voltage Protection (OVP) is measured in closed loop using the typical application circuit . The OVP value is found by forcing
an open circuit in the LED1 and LED2 path and recording the peak value of V_OUT. The value given in the Electrical Table is found in an open loop configuration
by ramping the voltage at OUT until the OVP comparator trips. The closed loop data can appear higher due to the stored energy in the inductor being dumped
into the output capacitor after the OVP comparator trips. At worst case is an open circuit condition where the output voltage can continue to rise after the OVP
comparator trips by approximately I_IN×sqrt(L/C_OUT).
Note 10: Guaranteed by design, not production tested.
Note 11: The timeout period is a divided down representation of the 2MHz clock and thus the accuracy spec is the same as the switching frequency.
Note 12: Min rise and fall times on SDA and SCL can typically be less than 20 ns.
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