DS99R105_14 Datasheet, PDF (6/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R105, DS99R106
SNLS242D – MARCH 2007 – REVISED APRIL 2013
www.ti.com
Serializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
t_HZD
DOUT ± HIGH to TRI-STATE Delay
t_LZD
DOUT ± LOW to TRI-STATE Delay
t_ZHD
DOUT ± TRI-STATE to HIGH Delay
t_ZLD
DOUT ± TRI-STATE to LOW Delay
t_PLD
Serializer PLL Lock Time
t_SD
Serializer Delay
R_L = 100Ω,
C_L = 10 pF to GND
(Figure 7)⁽²⁾
R_L = 100Ω, (Figure 8)
R_L = 100Ω, (Figure 9)
VODSEL = L, TRFB = H
R_L = 100Ω, (Figure 9)
VODSEL = L, TRFB = L
TxOUT_E_O TxOUT_Eye_Opening
(respect to ideal)
3–40 MHz
(Figure 10)^{(3) (4)}
Typ
10
3.5T +
2.85
3.5T +
2.85
0.68
Max
15
15
200
200
3.5T +
10
3.5T +
10
Units
ns
ns
ns
ns
ms
ns
ns
UI
(5)
(2) When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
(3) t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
(4) TxOUT_E_O is affected by pre-emphasis value.
(5) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Pin/Freq.
Min
Typ
Max
t_RCP
Receiver out Clock Period
t_RCP = t_TCP ⁽¹⁾
RCLK
25
T
333
t_RDC
RCLK Duty Cycle
RCLK
45
50
55
t_CLH
LVCMOS Low-to-High
Transition Time
t_CHL
LVCMOS High-to-Low
Transition Time
C_L = 8 pF
(lumped load)
(Figure 12)
ROUT [23:0],
LOCK, RCLK
2.5
3.5
2.5
3.5
t_ROS
t_ROH
t_ROS
t_ROH
t_ROS
t_ROH
t_HZR
t_LZR
t_ZHR
t_ZLR
t_DD
ROUT (7:0) Setup Data to RCLK
(Group 1)
ROUT (7:0) Hold Data to RCLK
(Group 1)
ROUT (15:8) Setup Data to RCLK
(Group 2)
ROUT (15:8) Hold Data to RCLK
(Group 2)
ROUT (23:16) Setup Data to
RCLK (Group 3)
ROUT (23:16) Hold Data to RCLK
(Group 3)
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
(Figure 16)
(Figure 16)
(Figure 16)
(Figure 14)
(Figure 13)
ROUT [7:0]
ROUT [15:8],
LOCK
ROUT [23:16]
ROUT [23:0],
RCLK, LOCK
RCLK
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(29/56)*t_RCP
(27/56)*t_RCP
0.5*t_RCP
0.5*t_RCP
(27/56)*t_RCP
(29/56)*t_RCP
3
3
3
3
[4+(3/56)]T
+5.9
10
10
10
10
[4+(3/56)]T
+18.5
t_DRDL
Deserializer PLL Lock Time from
Powerdown
RxIN_TOL_L Receiver INput TOLerance Left
RxIN_TOL_R Receiver INput TOLerance Right
(Figure 15)
(2) (1)
(Figure 17) ^{(3) (1) (4)}
(Figure 17) ^{(3) (1) (4)}
3 MHz
40 MHz
3 MHz–40 MHz
3 MHz–40 MHz
5
50
5
50
0.25
0.25
Units
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
UI
UI
(1) Specification is ensured by characterization and is not tested in production.
(2) The Deserializer PLL lock time (t_DRDL) may vary depending on input data patterns and the number of transitions within the pattern.
(3) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see TI’s AN-1217 (SNLA053) for detail.
(4) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
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