DS99R105_14 Datasheet, PDF (10/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R105, DS99R106
SNLS242D – MARCH 2007 – REVISED APRIL 2013
Deserializer
8 pF
lumped
Single-ended
Signal
80%
20%
80%
20%
t_CLH
t_CHL
Figure 12. Deserializer LVCMOS/LVTTL Output Load and Transition Times
RIN0-23
DCA, DCB
START
STOP START
STOP START
STOP START
STOP
BIT _{SYMBOL N} BIT BIT _{SYMBOL N+1} BIT BIT _{SYMBOL N+2} BIT BIT _{SYMBOL N+3} BIT
012
23
012
23
012
23
012
23
t_DD
RCLK
ROUT0-23
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
See Serializer Timing Requirements for TCLK Note (1).
Figure 13. Deserializer Delay
SYMBOL N
REN
500:
VREF
C_L = 8pF
+
-
VREF = V_DD/2 for t_ZLR or t_LZR,
VREF = 0V for t_ZHR or t_HZR
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VOH
REN
VOL
V_DD/2
t_LZR
V_DD/2
t_ZLR
VOL
ROUT [23:0]
VOH
t_HZR
VOL + 0.5V
t_ZHR
VOL + 0.5V
VOH - 0.5V
VOH + 0.5V
Note: C_L includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
Figure 14. Deserializer TRI-STATE Test Circuit and Timing
10
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