DS99R105_14 Datasheet, PDF (12/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R105, DS99R106
SNLS242D – MARCH 2007 – REVISED APRIL 2013
Ideal Data Bit
Beginning
Sampling
Window
Ideal Data Bit
End
RxIN_TOL -L
RxIN_TOL -R
Ideal Sampling Position
( )tBIT
2
t_BIT
(1UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
TxOUT_E_O is affected by pre-emphasis value.
Figure 17. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
DS99R105 Pin Diagram
Top View
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DIN[10]
37
DIN[11]
38
DIN[12]
39
DIN[13]
40
DIN[14]
41
V_DDIT
42
V_SSIT
43
DIN[15]
44
DIN[16]
45
DIN[17]
46
DIN[18]
47
DIN[19]
48
DS99R105
48 PIN WQFN
48 PIN TQFP
24
V_SS
23
PRE
22
V_DDDR
21
V_SSDR
20
DOUT+
19
DOUT-
18
DEN
17
V_SSPT0
16
V_DDPT0
15
V_SSPT1
14
V_DDPT1
13
RESRVD
Figure 18. Serializer - DS99R105
See Package Numbers NJU0048D and PFB0048A
12
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