DS99R105_14 Datasheet, PDF (2/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R105, DS99R106
SNLS242D – MARCH 2007 – REVISED APRIL 2013
Block Diagram
PRE (on/off)
DEN
VODSEL
REN
24
D_IN
TRFB
D_OUT+
D_OUT-
R_IN+
R_IN-
24
R_OUT
TCLK
TPWDNB
PLL
Timing
and
Control
RRFB
RPWDNB
PLL
Timing
and
Control
Clock
Recovery
LOCK
RCLK
SERIALIZER ± DS99R105
DESERIALIZER ± DS99R106
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Figure 1.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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