DS99R105_14 Datasheet, PDF (11/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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2.0V
PWDN
RIN±
LOCK TRI-STATE
ROUT [0:23]
RCLK
t_DRDL
TRI-STATE
TRI-STATE
DS99R105, DS99R106
SNLS242D – MARCH 2007 – REVISED APRIL 2013
0.8V
}v[š Œ
TRI-STATE
t_HZR or t_LZR
TRI-STATE
TRI-STATE
REN
See Serializer Timing Requirements for TCLK Note (1).
Figure 15. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
RCLK
V_DD/2
t_LOW
t_HIGH
V_DD/2
ROUT [7:0]
t_ROS
(group 1)
V_DD/2
Data Valid
Before RCLK
t_ROH
(group 1)
Data Valid
After RCLK
V_DD/2
1/2 UI
t_ROS
(group 2)
ROUT [15:8], LOCK
V_DD/2
Data Valid
Before RCLK
t_ROH
(group 2)
1/2 UI
Data Valid
After RCLK
V_DD/2
1/2 UI
t_ROS
(group 3)
ROUT [23:16]
V_DD/2
Data Valid
Before RCLK
t_ROH
(group 3)
1/2 UI
Data Valid
After RCLK
V_DD/2
See Serializer Timing Requirements for TCLK Note (2).
Figure 16. Deserializer Setup and Hold Times
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