DS64EV100_14 Datasheet, PDF (6/15 Pages) Texas Instruments – Programmable Single Equalizer

DS64EV100
SNLS232D – OCTOBER 2007 – REVISED APRIL 2008
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IN+
IN-
BST_0 : BST_2
Input
Termination
DC Offset Correction
Equalizer
BST CNTL
Limiting
Amplifier
3
3
OUT +
OUT-
Figure 6. Simplified Block Diagram
EQUALIZER BOOST CONTROL
The equalizer channel supports eight programmable levels of equalization boost, and is controlled by the Boost
Set pins (BST_[2:0]) in accordance with Table 1. The eight levels of boost settings enables the DS64EV100 to
address a wide range of media loss and data rates.
6 mil Microstrip FR4
Trace Length (in)
0
5
10
15
20
25
30
40
Table 1. EQ Boost Control Table
24 AWG Twin-AX Cable
Length (m)
0
2
3
4
5
6
7
10
Channel Loss at 3.2 GHz
(db)
0
5
7.5
10
12.5
15
17
22
Channel Loss at 5 GHz
(dB)
0
6
10
14
18
21
24
30
BST_N
[2, 1, 0]
000
001
010
011
1 0 0 (Default)
101
110
111
GENERAL RECOMMENDATIONS
The DS64EV100 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner’s Manual for more detailed information on high-speed design tips to address signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML
lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of
a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit
board. See AN-1187 for additional information on LLP packages.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS64EV100 is provided with an adequate power supply.
First, the supply (V_DD) and ground (GND) pins should be connected to power planes routed on adjacent layers of
the printed circuit board. The layer thickness of the dielectric should be minimized so that the V_DD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01μF bypass capacitor should be
connected to each V_DD pin such that the capacitor is placed as close as possible to the DS64EV100. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as
possible to the DS64EV100.
6
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