DS64EV100_14 Datasheet, PDF (5/15 Pages) Texas Instruments – Programmable Single Equalizer

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Timing Diagrams
DS64EV100
SNLS232D – OCTOBER 2007 – REVISED APRIL 2008
Signal Source
A
B
C
6 mils Trace Width,
FR4 Microstrip Test Channel
SMA
Connector
SMA
Connector
DS64EV100
INPUT
OUTPUT
Figure 2. Test Setup Diagram
80%
OUT diff = (OUT+) ± (OUT-)
0V
20%
80%
20%
t_R
t_F
Figure 3. CML Output Transition Times
IN diff
0V
t_PLHD
OUT diff
0V
t_PHLD
Figure 4. Propagation Delay Timing Diagram
V_DD
10k
IN +
50
6k
V_DD
EQ
50
10k
IN -
6k
Figure 5. Simplified Receiver Input Termination Circuit
DS64EV100 Applications Information
The DS64EV100 is a programmable equalizer optimized for operation up to 10 Gbps for backplane and cable
applications. The equalizer channel consists of an equalizer stage, a limiting amplifier, a DC offset correction
block, and a CML driver as shown in Figure 5.
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Links: DS64EV100
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