DS64EV100_14 Datasheet, PDF (4/15 Pages) Texas Instruments – Programmable Single Equalizer

DS64EV100
SNLS232D – OCTOBER 2007 – REVISED APRIL 2008
www.ti.com
Symbol
Parameter
Conditions
V_OH
High Level Output
I_OH = –3 mA, V_DD3.3
Voltage
I_OH = –3 mA, V_DD2.5
V_OL
Low Level Output
I_OL = 3 mA
Voltage
I_IN
Input Current
V_IN = V_DD
V_IN = GND
I_IN-P
Input Leakage
V_IN = GND, with internal pull-down resistors
Current with Internal
Pull-Down/Up
V_IN = GND, with internal pull-up resistors
Resistors
CML RECEIVER INPUTS (IN+, IN−)
V_TX
Source Transmit
AC-Coupled or DC-Coupled Requirement,
Launch Signal Level Differential measurement at point A.
(IN diff)
(Figure 1)
V_INTRE
Input Threshold
Voltage
Differential measurement at point B .
(Figure 1)
V_DDTX
Supply Voltage of
Transmitter to EQ
DC-Coupled Requirement
V_ICMDC
Input Common-Mode DC-Coupled Requirement Differential
Voltage
measurement at point A.
(Figure 1), (Note 7)
R_LI
Differential Input
100 MHz – 3.2 GHz, with fixture’s effect de-
Return Loss
embedded
R_IN
Input Resistance
CML OUTPUTS (OUT+, OUT−)
Differential Across IN+ and IN-. (Figure 4)
V_OD
Output Differential Differential measurement with OUT+ and OUT-
Voltage Level (OUT terminated by 50Ω to GND, AC-Coupled
diff)
(Figure 2)
V_OCM
Output Common-
Mode Voltage
Single-ended measurement DC-Coupled with
50Ω terminations
(Note 7)
t_R, t_F
Transition Time
20% to 80% of differential output voltage,
measured within 1” from output pins.
(Figure 2)
(Note 7)
R_O
Output Resistance Single-ended to V_DD
R_LO
Differential Output 100 MHz – 1.6 GHz, with fixture’s effect de-
Return Loss
embedded. IN+ = static high.
t_PLHD
Differential Low to
High Propagation
Delay
Propagation delay measurement at 50% V_OD
between input to output, 100 Mbps
(Figure 3), (Note 7)
t_PHLD
Differential High to
Low Propagation
Delay
EQUALIZATION
DJ1
Residual
30” of 6 mil microstrip FR4, EQ Setting 0x06,
Deterministic Jitter at PRBS-7 (2⁷-1) pattern
10 Gbps
(Note 5, 6)
DJ2
Residual
40” of 6 mil microstrip FR4, EQ Setting 0x06,
Deterministic Jitter at PRBS-7 (2⁷-1) pattern
6.4 Gbps
(Note 5, 6)
DJ3
Residual
40” of 6 mil microstrip FR4, EQ Setting 0x07,
Deterministic Jitter at PRBS-7 (2⁷-1) pattern
5 Gbps
(Note 5, 6)
DJ4
Residual
40” of 6 mil microstrip FR4, EQ Setting 0x07,
Deterministic Jitter at PRBS-7 (2⁷-1) pattern
2.5 Gbps
(Note 5, 6)
RJ
Random Jitter
(Note 7, 8)
Min
2.4
2.0
−15
–20
400
1.6
V_DDTX-0.8
85
550
V_DD-0.2
20
42
Typ
(1)
+1.8
0
+95
Max
Units
V
V
0.4
V
+15
µA
µA
µA
µA
1600
mV_P-P
120
mV_P-P
V_DD
V
V_DDTX-0.2
V
10
dB
100
115
Ω
620
725
mV_P-P
V_DD-0.1
V
60
ps
50
58
Ω
10
dB
240
ps
240
ps
0.20
0.17
0.12
0.10
0.5
0.26
0.20
0.16
UI_P-P
UI_P-P
UI_P-P
UI_P-P
ps_rms
4
Submit Documentation Feedback
Product Folder Links: DS64EV100
Copyright © 2007–2008, Texas Instruments Incorporated