DRV8804_16 Datasheet, PDF (6/27 Pages) Texas Instruments – Quad Serial Interface Low-Side Driver IC

DRV8804
SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015
6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
1
t_CYC
2
t_CLKH
3
t_CLKL
4
t_SU(SDATIN)
5
t_H(SDATIN)
6
t_D(SDATOUT)
7
t_W(LATCH)
8
t_OE(ENABLE)
9
t_D(LATCH)
—
t_RESET
10
t_D(RESET)
11
t_STARTUP
(1) Not production tested.
Clock cycle time
Clock high time
Clock low time
Setup time, SDATIN to SCLK
Hold time, SDATIN to SCLK
Delay time, SCLK to SDATOUT, no external pullup resistor,
C_OUT = 100 pF
Pulse width, LATCH
Enable time, nENBL to output low
Delay time, LATCH to output change
RESET pulse width
Reset delay before clock
Start-up delay VM applied before clock
RESET
VM
SCLK
SDATIN
10
11
1
2
3
Data in
valid
nENBL
LATCH
OUTx
SDATOUT
45
Data out valid
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MIN NOM MAX
62
25
25
5
1
50 100
200
60
200
20
20
55
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
7
8
9
6
More than 400 ns of delay should exist between the final SCLK rising edge and the LATCH rising edge. This ensures
that the last data bit is shifted into the device properly.
Figure 1. DRV8804 Timing Requirements
6
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