DRV8804_16 Datasheet, PDF (10/27 Pages) Texas Instruments – Quad Serial Interface Low-Side Driver IC

DRV8804
SLVSAW4F – JULY 2011 – REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
7.3.3 nENBL and RESET Operation
The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does
not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown.
The RESET pin, when driven active high, resets internal logic, including the OCP fault. All serial interface
registers are cleared. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so
driving RESET at power up is not required.
7.3.4 Protection Circuits
The DRV8804 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.4.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the t_OCP deglitch time (approximately 3.5 µs), the driver will be
disabled and the nFAULT pin will be driven low. The driver will remain disabled for the t_RETRY retry time
(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
RESET pin is activated or VM is removed and re-applied.
7.3.4.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume.
7.3.4.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout (UVLO) threshold voltage, all
circuitry in the device will be disabled, and internal logic will be reset. Operation will resume when V_M rises above
the UVLO threshold.
7.4 Device Functional Modes
When the nENBL pin of the DRV8804 is pulled logic low, the open-drain FET outputs are enabled. Having the
device be enabled at logic low allows for the use of long data lines in a high noise environment that do not
unintentionally enable the device with coupled noise. The device will still shift data through the SDATIN /
SDATOUT lines and SCLK line regardless of the state of the nENBL pin.
Once data has been moved into each of the four shift register lines the LATCH pin can be pulled high to output
the state of the four shift registers. Once LATCH is pulled high the state of the four shift registers is placed in a
logical AND with the inverse state of the nENBL pin. If the nENBL pin is logic low input and the LATCH pin is
logic high the open-drain output of that driver channel will be turned on.
If the device detects that V_M has dropped below the UVLO threshold, it will immediately enter a state where all
the internal logic is disabled. The device stays in a disabled state until V_M rises above the UVLO threshold and
all internal logic is then reset. During an Overcurrent Protection (OCP) event the device removes gate drive for
one t_RETRY interval and the nFAULT pin is driven low. The fault is cleared immediately if RESET is activated or
V_M is removed and re-applied.
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