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| DAC8551-Q1 Datasheet, PDF (6/28 Pages) Texas Instruments – Automotive 16-Bit, Ultralow-Glitch, Voltage-Output DAC | |||
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DAC8551-Q1
SLASEB8A â FEBRUARY 2016 â REVISED MARCH 2016
www.ti.com
6.6 Timing Requirements(1)(2)
VDD = 3.2 V to 5.5 V and TA = â40°C to 125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN NOM MAX
fSCLK Serial clock frequency
t1
SCLK cycle time
t2
SCLK high time
t3
SCLK low time
t4 SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7 24th SCLK falling edge to SYNC rising edge
t8
Minimum SYNC high time
t9 24th SCLK falling edge to SYNC falling edge
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 3.6 V
VDD = 3.6 V to 5.5 V
VDD = 3.2 V to 5.5 V
25
30
40
34
13
13
22.5
13
0
0
5
5
5
5
0
0
50
34
50
(1) All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) See the Serial-Write-Operation Timing Diagram.
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.7 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Power-up time
Coming out of power-down mode,
VDD = 5 V
Coming out of power-down mode,
VDD = 3.3 V
MIN
TYP
MAX UNIT
2.5
µs
5
SCLK
SYNC
DIN
1
t8
t4
t1
t9
24
t3
t2
t7
DB23
t6
t5
DB0
DB23
Figure 1. Serial-Write-Operation Timing Diagram
6
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Copyright © 2016, Texas Instruments Incorporated
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