DAC8551-Q1 Datasheet, PDF (15/28 Pages) Texas Instruments – Automotive 16-Bit, Ultralow-Glitch, Voltage-Output DAC

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DAC8551-Q1
SLASEB8A – FEBRUARY 2016 – REVISED MARCH 2016
7.5 Programming
The DAC8551-Q1 has a 3-wire serial interface (SYNC, SCLK, and D_IN), which is compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs. See the Serial Write Operation Timing Diagram section for
an example of a typical write sequence.
The input shift register is 24 bits wide, as shown in Figure 30. The first six bits are don't care bits. The next two
bits (PD1 andPD0) are control bits that control which mode of operation the part is in (normal mode or any one of
three power-down modes). A more complete description of the various modes is located in the Power-Down
Modes section. The next 16 bits are the data bits. These bits are transferred to the DAC register on the 24th
falling edge of SCLK.
DB23
DB0
X X X X X X PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 30. DAC8551-Q1 Data-Input Register Format
The write sequence begins by bringing the SYNC line low. Data from the D_IN line are clocked into the 24-bit shift
register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the
DAC8551-Q1 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is
clocked in and the programmed function is executed (that is, a change in DAC register contents and/or a change
in the mode of operation).
At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write
sequence. As previously mentioned, it must be brought high again just before the next write sequence.
7.5.1 SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, it acts as an
interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an
update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 31.
CLK
SYNC
24th Falling Edge
24th Falling Edge
D_IN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 31. SYNC Interrupt Facility
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