DAC8551-Q1 Datasheet, PDF (19/28 Pages) Texas Instruments – Automotive 16-Bit, Ultralow-Glitch, Voltage-Output DAC

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DAC8551-Q1
SLASEB8A – FEBRUARY 2016 – REVISED MARCH 2016
8.3 System Examples
8.3.1 Interface from DAC8551-Q1 to 8051
See Figure 37 for a serial interface between the DAC8551-Q1 and a typical 8051-type microcontroller. The setup
for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8551-Q1, while RXD drives the serial
data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this
case, port line P3.3 is used. When data are to be transmitted to the DAC8551-Q1, P3.3 is taken low. The 8051
transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted, then a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs the
serial data in a format that has the LSB first. The DAC8551-Q1 requires data with the MSB as the first bit
received. The 8051 transmit routine must therefore take this into account, and mirror the data as needed.
80C51 or 80L51⁽¹⁾
P3.3
TXD
RXD
DAC8551-Q1⁽¹⁾
SYNC
SCLK
D_IN
NOTE: (1) Additional pins omitted for clarity.
Figure 37. Interface from DAC8551-Q1 Devices to 80C51 or 80L51
8.3.2 Interface from DAC8551-Q1 to Microwire
Figure 38 shows an interface between the DAC8551-Q1 and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and is clocked into the DAC8551-Q1 on the rising edge of the
SK signal.
Microwire^TM
CS
DAC8551-Q1⁽¹⁾
SYNC
SK
SCLK
SO
D_IN
NOTE: (1) Additional pins omitted for clarity.
Figure 38. Interface from DAC8551-Q1 Devices to Microwire
8.3.3 Interface from DAC8551-Q1 to 68HC11
Figure 39 shows a serial interface between the DAC8551-Q1 and the 68HC11 microcontroller. SCK of the
68HC11 drives the SCLK of the DAC8551-Q1, whereas the MOSI output drives the serial data line of the DAC.
The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.
68HC11⁽¹⁾
PC7
SCK
MOSI
DAC8551-Q1⁽¹⁾
SYNC
SCLK
D_IN
NOTE: (1) Additional pins omitted for clarity.
Figure 39. Interface from DAC8551-Q1 Devices to 68HC11
The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration causes
data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to
the DAC, the SYNC line is held low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to
the DAC88551-Q1, PC7 is left low after the first eight bits are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken high at the end of this procedure.
Copyright © 2016, Texas Instruments Incorporated
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