CDC3RL02_16 Datasheet, PDF (6/20 Pages) Texas Instruments – Low Phase-Noise Two-Channel Clock Fan-Out Buffer

CDC3RL02
SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MCLK_IN SINUSOIDAL SOURCE
V_MA
Input amplitude
1-kHz offset
10-kHz offset
f_IN = 26 MHz, V_MA = 1.8 V_{PP 100-kHz offset}
Additive phase noise
1-MHz offset
1-kHz offset
10-kHz offset
f_IN = 26 MHz, V_MA = 0.8 V_{PP 100-kHz offset}
1-MHz offset
Additive jitter
t_DS
MCLK_IN to CLK_OUT_1/2
propagation delay
f_IN = 26 MHz, V_MA = 1.8 V_PP, BW = 10–5 MHz
DC_s
Output duty cycle
CLK_OUT_N OUTPUTS
f_IN = 26 MHz, V_MA > 1.8 V_PP
t_r
20% to 80% rise time
t_f
20% to 80% fall time
t_sk
Channel-to-channel skew
V_OH
High-level output voltage
V_OL
Low-level output voltage
C_L = 10 pF to 50 pF
C_L = 10 pF to 50 pF
C_L = 10 pF to 50 pF (C_L1 = C_L2)
I_OH = –100 μA, reference to V_LDO
I_OH = –8 mA
I_OL = 20 μA
I_OL = 8 mA
www.ti.com
MIN TYP MAX UNIT
0.3
–141
–149
–152
–148
–139
–146
–150
–146
0.41
12
45% 50%
1.8 V
dBc/Hz
ps (RMS)
ns
55%
1
5.2 ns
1
5.2 ns
–0.5
0.5 ns
–0.1
V
1.2
0.2
V
0.55
6
Submit Documentation Feedback
Product Folder Links: CDC3RL02
Copyright © 2009–2016, Texas Instruments Incorporated