CDC3RL02_16 Datasheet, PDF (4/20 Pages) Texas Instruments – Low Phase-Noise Two-Channel Clock Fan-Out Buffer

CDC3RL02
SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted. ⁽¹⁾
V_BATT
I_IK
I_O
T_J
T_A
T_stg
Voltage range⁽²⁾
Voltage range⁽³⁾
Input clamp current at V_BATT,
CLK_REQ_1/2, and MCLK_IN
CLK_REQ_1/2, MCLK_IN
V_LDO, CLK_OUT_1/2⁽²⁾
V_I < 0
Continuous output current
CLK_OUT1/2
Continuous current through GND, V_BATT, V_LDO
Operating virtual junction temperature
Operating ambient temperature range
Storage temperature range
MIN
–0.3
–0.3
–0.3
–40
–40
–55
MAX
7
V_BATT + 0.3
V_BATT + 0.3
–50
±20
±50
150
85
150
UNIT
V
V
mA
mA
mA
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) All voltage values are with respect to network ground pin.
7.2 ESD Ratings
V_(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
Machine Model
VALUE
±2000
±1000
200
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
See ⁽¹⁾
V_BATT
V_I
V_O
V_IH
V_IL
I_OH
I_OL
Input voltage to internal LDO
Input voltage
Output voltage
High-level input voltage
Low-level input voltage
High-level output current, DC current
Low-level output current, DC current
MCLK_IN, CLK_REQ1/2
CLK_OUT1/2
CLK_REQ1/2
CLK_REQ1/2
MIN
MAX
2.3
5.5
0
1.89
0
1.8
1.3
1.89
0
0.5
–8
8
(1) All unused inputs of the device must be held at V_CC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
UNIT
V
V
V
V
V
mA
mA
4
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