CDC3RL02_16 Datasheet, PDF (13/20 Pages) Texas Instruments – Low Phase-Noise Two-Channel Clock Fan-Out Buffer

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CDC3RL02
SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
9.2.3 Application Curves
2.4
2.2
V_BATT = 3.3 V C_VLDO = 1 µF
C_BATT = 0.1 µF C_OUT = 30 pF
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2 MCLK_IN
CLK_OUT1
-0.4
0 10 20 30 40 50 60 70 80 90 100
Tim e (ns)
Figure 13. Sine Wave Input vs Output
10 Power Supply Recommendations
General power supply recommendations are to be considered for the CDC3RL02. These include:
• Decoupling capacitors placed close to the V_BATT pin of typical values (1 μF)
• V_BATT be within the recommended voltage range
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies and should be placed as close as possible to the V_BATT
pin
• Short trace-lengths should be used to avoid excessive loading
• For improved performance on the clock output lines, use a ground trace on the sides of the clock trace to
minimize crosstalk and EMI
11.2 Layout Example
0402 Decoupling
Cap
V_BATT
A1
V_LDO
MCLK_IN
GND
CLK_OUT1
CLK_REQ1
CLK_REQ2
= Via to GND Plane
= GND Trace
CLK_OUT2
Figure 14. Example Layout for YFP Package
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