CDC3RL02_16 Datasheet, PDF (12/20 Pages) Texas Instruments – Low Phase-Noise Two-Channel Clock Fan-Out Buffer

CDC3RL02
SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
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9.2 Typical Application
The CDC3RL02 is ideal for use in mobile applications as shown in Figure 12. In this example, a single low noise
TCXO system clock source is buffered to drive a mobile GPS receiver and WLAN transceiver. Each peripheral
independently requests an active clock by asserting a single clock request line (CLK_REQ_1 or CLK_REQ_2).
When both clock request lines are inactive, the CDC3RL02 enters a low current shutdown mode. In this mode,
the LDO output, CLK_OUT_1, and CLK_OUT_2 are pulled to GND and the TCXO will be unpowered.
2.2 µF
TCXO
V_LDO
LDO
V_BATT
MCLK_IN
CLK_REQ_1
CLK_OUT_1
CLK_REQ_2
CLK_OUT_2
CDC3RL02 _GND
1 µF
Li
GPS
TCXO REQ
TCXO CLK
TCXO REQ
TCXO CLK
WLAN
Figure 12. Mobile Application
When either peripheral requests the clock, the CDC3RL02 will enable the LDO and power the TCXO. The TCXO
output (square wave, sine wave, or clipped sine wave) is converted to a square wave and buffered to the
requested output.
9.2.1 Design Requirements
For the typical application, the user must know the following parameters.
PARAMETER
V_BATT
MCLK_IN
Table 2. Design Parameters
DESCRIPTION
Input voltage from battery or power supply
Input frequency from a TCXO
EXAMPLE VALUE
3.7 V
26 MHz
9.2.2 Detailed Design Procedure
The designer must make sure that all parameters are within the ranges specified in Recommended Operating
Conditions.
Each device which receives a clock output from the CDC3RL02 should have the CLK request pin connected to
the appropriate CLK_REQ pin on the CDC3RL02. This will enable the output buffer when a device requests the
clock signal.
It is possible to have a control the outputs of the clock by using a GPIO from a controller to control the CLK_REQ
pins.
If one of the outputs is unused, then tie the CLK_REQ and CLK_OUT pins to ground. If the clock will always be
required, and the user wishes, it is acceptable to tie the CLK_REQ pin to a 1.8 V source (such as V_LDO).
12
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