CDC3RL02_16 Datasheet, PDF (3/20 Pages) Texas Instruments – Low Phase-Noise Two-Channel Clock Fan-Out Buffer

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5 Device Comparison Table
CDC3RL02
SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
T_A
-40 C to 85 C
-40 C to 85 C
PACKAGE ⁽¹⁾
YFP
YFP
ORDERABLE PART NUMBER
CDC3RL02BYFPR
CDC3RL02YFPR
BACKSIDE
COATING ⁽²⁾
Yes
No
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) CSP (DSBGA) devices manufactured with backside coating have an increased resistance to cracking due to the increased physical
strength of the package. Devices with backside coating are highly encouraged for new designs.
6 Pin Configuration and Functions
YFP Package
8-Pin DSBGA
Top View
12
A
A1 A2
B
B1 B2
C
C1 C2
D
D1 D2
PIN
NAME
NO.
V_BATT
A1
CLK_OUT1
A2
V_LDO
B1
CLK_REQ1
B2
MCLK_IN
C1
CLK_REQ2
C2
GND
D1
CLK_OUT2
D2
A
B
C
D
Pin Functions
I/O
DESCRIPTION
I
Input to internal LDO
O
Clock output 1
O
1.8 V I/O supply for CDC3RL02 and external TCXO
I
Clock request from peripheral 2
I
Master clock input
I
Clock request from peripheral 1
–
Ground
O
Clock output 2
YFP Package Pin Assignments
1
V_BATT
V_LDO
MCLK_LIN
GND
2
CLK_OUT1
CLK_REQ1
CLK_REQ2
CLK_OUT2
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