BQ24273 Datasheet, PDF (6/27 Pages) Texas Instruments – 2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Integrated Current Sense

bq24273
SLUSB08 – JUNE 2012
PIN CONFIGURATION
49-Ball WCSP (Top View)
1
2
3
4
5
6
7
A
IN
IN
IN
IN
GND
GND
GND
B
PMIDI
PMIDI
PMIDI
PMIDI
BYP
BYP
BYP
C
SW
SW
SW
SW
SW
SW
SW
D
PGND
PGND
PGND
PGND
PGND
PGND
PGND
E
PGND
N.C.
N.C.
CD
SDA
SCL
BOOT
CS+
F
BAT
G
CS+
CS+
CS+
N.C.
INT
DRV
BAT
BAT
BAT
TS
STAT
PGND
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NAME
IN
GND
PMID
BYP
SW
PGND
N.C.
CD
SDA
SCL
BOOT
CS+
INT
DRV
BAT
PIN FUNCTIONS
PIN
bq24273 (YFF) I/O DESCRIPTION
A1-A4
I
Input Power Supply. IN is connected to the external DC supply (AC adapter). Bypass IN to PGND
with at least a 1μF ceramic capacitor.
A5-A7
I Ground. Connect to ground plane.
B1-B4
Reverse Blocking MOSFET and High Side MOSFET Connection Point for the input. Bypass PMID
O to GND with at least a 4.7μF ceramic capacitor. Use caution when connecting an external load to
PMID. The PMID output is not current limited. Any short on PMID will result in damage to the IC.
B5-B7
O
Bypass for internal circuits. Bypass BYP to GND with at least 0.1µF of capacitance. Do not
connect any external load to BYP.
C1-C7
O Inductor Connection. Connect to the switched side of the external inductor.
D1-D7, E1, G7 -- Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
E2-E3, F5
No Connection. Leave N.C. unconnected.
E4
IC Hardware Disable Input – Drive CD high to place the bq24273 in high-z mode. Drive CD low for
normal operation. Do not leave CD unconnected.
E5
I²C Interface Data – Connect SDA to the logic rail through a 10kΩ resistor.
E6
I²C Interface Clock – Connect SCL to the logic rail through a 10kΩ resistor.
E7
I
High Side MOSFET Gate Driver Supply. Connect a 0.01μF ceramic capacitor (voltage rating >
10V) from BOOT to SW to supply the gate drive for the high side MOSFETs.
F1-F4
I
Current Sense Input. High side connection to internal current sense element. Bypass CS+ locally
with at least 10µF of ceramic capacitance for stability.
Status Output – INT is an open-drain output that signals charging status and fault interrupts. INT
pulls low during charging. INT is high impedance when charging is complete or the charger is
F6
disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is
enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through
a 100kΩ resistor to communicate with the host processor
F7
G1-G4
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. bypass
O DRV to PGND with a 1μF ceramic capacitor. DRV may be used to drive external loads up to
10mA. DRV is active whenever the input is connected and _VIN > V_UVLO and V_IN > (V_BAT + V_SLP)
I/O
Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to
GND with a 1μF capacitor.
6
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