BQ24273 Datasheet, PDF (16/27 Pages) Texas Instruments – 2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Integrated Current Sense

bq24273
SLUSB08 – JUNE 2012
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high ( see Figure 9). This releases the bus and stops the communication
link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section result in FFh being read out.
Data output
by Transmitter
Data output
by Receiver
Not Acknowledge
Acknowledge
SCL From
Master
S
START
Condition
1
2
8
Figure 8. Acknowledge on the I2C Bus
9
Clock Pulse for
Acknowledgement
Recognize START or
REPRATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
Recognize STOP or
REPRATED START
Condition
P
Sr
R/W
SCL
S
or
Sr
1
2
7
8
9
1
2
3-8
9
Sr
ACK
ACK
or
P
Clock Line Held Low While
Interrupts are Serviced
Figure 9. Bus Protocol
16
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