BQ24273 Datasheet, PDF (15/27 Pages) Texas Instruments – 2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Integrated Current Sense

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bq24273
SLUSB08 – JUNE 2012
SERIAL INTERFACE DESCRIPTION
The bq24273 uses an I²C compatible interface to program charge parameters. I²C™ is a 2-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C compatible devices connect to the I²C bus through open drain I/O pins, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device.
The bq24273 device works as a slave and supports the following data transfer modes, as defined in the I²C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charging solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as battery voltage remains
above 2.5 V (typical). The I²C circuitry is powered from IN when a supply is connected. If the IN supply is not
connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must stay above 2.5V
with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24273 devices only support 7-bit addressing. The device 7-bit address is
defined as ‘1101011’ (6Bh).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 6. All I²C -compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 6. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 7). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 8) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 7. Bit Transfer on the Serial Interface
Copyright © 2012, Texas Instruments Incorporated
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