TM4C123BH6PZ Datasheet, PDF (598/1311 Pages) Texas Instruments – Tiva TM4C123BH6PZ Microcontroller

Micro Direct Memory Access (μDMA)
9.3.2.3
9.3.3
9.3.3.1
Table 9-8. Channel Control Word Configuration for Memory Transfer Example
Field in DMACHCTL
DSTINC
DSTSIZE
SRCINC
SRCSIZE
reserved
ARBSIZE
XFERSIZE
NXTUSEBURST
XFERMODE
Bits
31:30
29:28
27:26
25:24
23:18
17:14
13:4
3
2:0
Value
2
2
2
2
0
3
255
0
2
Description
32-bit destination address increment
32-bit destination data size
32-bit source address increment
32-bit source data size
Reserved
Arbitrates after 8 transfers
Transfer 256 items
N/A for this transfer type
Use Auto-request transfer mode
Start the Transfer
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register.
2. Issue a transfer request by setting bit 30 of the DMA Channel Software Request (DMASWREQ)
register.
The μDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt
when the transfer is complete. If needed, the status can be checked by reading bit 30 of the
DMAENASET register. This bit is automatically cleared when the transfer is complete. The status
can also be checked by reading the XFERMODE field of the channel control word at offset 0x1E8.
This field is automatically cleared at the end of the transfer.
Configuring a Peripheral for Simple Transmit
This example configures the μDMA controller to transmit a buffer of data to a peripheral. The
peripheral has a transmit FIFO with a trigger level of 4. The example peripheral uses μDMA channel
7.
Configure the Channel Attributes
First, configure the channel attributes:
1. Configure bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
598
June 12, 2014
Texas Instruments-Production Data