TM4C123BH6PZ Datasheet, PDF (516/1311 Pages) Texas Instruments – Tiva TM4C123BH6PZ Microcontroller

Hibernation Module
Register 8: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Writing a 1 to a bit clears the corresponding interrupt in the HIBRIS register.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WC
EXTW LOWBAT reserved RTCALT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW1C RW1C RW1C
RO
RW1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:5
4
3
2
1
0
Name
reserved
WC
EXTW
LOWBAT
reserved
RTCALT0
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW1C
0
Write Complete/Capable Interrupt Clear
Writing a 1 to this bit clears the WC bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
RW1C
0
External Wake-Up Interrupt Clear
Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
RW1C
0
Low Battery Voltage Interrupt Clear
Writing a 1 to this bit clears the LOWBAT bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW1C
0
RTC Alert0 Masked Interrupt Clear
Writing a 1 to this bit clears the RTCALT0 bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
Note:
The timer interrupt source cannot be cleared if the RTC value
and the HIBRTCM0 register / RTCMSS field values are equal.
The match interrupt takes priority over the interrupt clear.
516
June 12, 2014
Texas Instruments-Production Data