TM4C123BH6PZ Datasheet, PDF (505/1311 Pages) Texas Instruments – Tiva TM4C123BH6PZ Microcontroller

Tiva^™ TM4C123BH6PZ Microcontroller
Register 3: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is used to load a 32-bit value loaded into the RTC counter. The load occurs immediately
upon this register being written. When this register is written, the 15-bit sub seconds counter is also
cleared.
Note:
The Hibernation module registers are on the Hibernation module clock domain and have
special timing requirements. Software should make use of the WRC bit in the HIBCTL register
to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted
write access is ignored. See “Register Access Timing” on page 491.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCLD
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCLD
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
RTCLD
Type
Reset Description
RW 0x0000.0000 RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
June 12, 2014
505
Texas Instruments-Production Data