TM4C123BH6PZ Datasheet, PDF (1006/1311 Pages) Texas Instruments – Tiva TM4C123BH6PZ Microcontroller

Inter-Integrated Circuit (I²C) Interface
Table 16-1. I2C Signals (100LQFP) (continued)
Pin Name
I2C3SDA
I2C4SCL
I2C4SDA
I2C5SCL
I2C5SDA
Pin Number Pin Mux / Pin
Assignment
2
PD1 (3)
61
PG1 (3)
60
PG2 (3)
59
PG3 (3)
87
PG6 (3)
88
PG7 (3)
Pin Type
I/O
I/O
I/O
I/O
I/O
Buffer Type^a Description
OD
I²C module 3 data.
OD
I²C module 4 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
OD
I²C module 4 data.
OD
I²C module 5 clock. Note that this signal has an
active pull-up. The corresponding port pin should
not be configured as open drain.
OD
I²C module 5 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
16.3
Functional Description
Each I²C module is comprised of both master and slave functions and is identified by a unique
address. A master-initiated communication generates the clock signal, SCL. For proper operation,
the SDA pin must be configured as an open-drain signal. Due to the internal circuitry that supports
high-speed operation, the SCL pin must not be configured as an open-drain signal, although the
internal circuitry causes it to act as if it were an open drain signal. Both SDA and SCL signals must
be connected to a positive supply voltage using a pull-up resistor. A typical I²C bus configuration is
shown in Figure 16-2. Refer to the I2C-bus specification and user manual to determine the size of
the pull-ups needed for proper operation.
See “Inter-Integrated Circuit (I²C) Interface” on page 1299 for I²C timing diagrams.
Figure 16-2. I²C Bus Configuration
SCL
SDA
RPUP
RPUP
I²C Bus
I2CSCL I2CSDA
Tiva™
Microcontroller
SCL
SDA
3rd Party Device
with I²C Interface
SCL
SDA
3rd Party Device
with I²C Interface
16.3.1
I²C Bus Functional Overview
The I²C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on TM4C123BH6PZ
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I²C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 1007) is unrestricted, but
each data byte has to be followed by an acknowledge bit, and data must be transferred MSB first.
When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force
the transmitter into a wait state. The data transfer continues when the receiver releases the clock
SCL.
1006
Texas Instruments-Production Data
June 12, 2014