TM4C123BH6PZ Datasheet, PDF (1036/1311 Pages) Texas Instruments – Tiva TM4C123BH6PZ Microcontroller

Inter-Integrated Circuit (I²C) Interface
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CLKMIS MIS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
0
Name
reserved
CLKMIS
MIS
Type
RO
RO
RO
Reset
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Timeout Masked Interrupt Status
Value Description
0 No interrupt.
1 An unmasked clock timeout interrupt was signaled and is
pending.
This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.
Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked master interrupt was signaled and is pending.
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
1036
Texas Instruments-Production Data
June 12, 2014