TMS320F28069_1107 Datasheet, PDF (57/172 Pages) Texas Instruments – Piccolo Microcontrollers

www.ti.com
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698B – NOVEMBER 2010 – REVISED JULY 2011
3.9.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of
the PLL (VCOCLK) is at least 50 MHz.
Table 3-16. PLL Settings
PLLCR[DIV] VALUE^{(1) (2)}
00000 (PLL bypass)
PLLSTS[DIVSEL] = 0 or 1⁽³⁾
OSCCLK/4 (Default)⁽¹⁾
SYSCLKOUT (CLKIN)
PLLSTS[DIVSEL] = 2
OSCCLK/2
PLLSTS[DIVSEL] = 3
OSCCLK
00001
(OSCCLK * 1)/4
(OSCCLK * 1)/2
(OSCCLK * 1)/1
00010
(OSCCLK * 2)/4
(OSCCLK * 2)/2
(OSCCLK * 2)/1
00011
(OSCCLK * 3)/4
(OSCCLK * 3)/2
(OSCCLK * 3)/1
00100
(OSCCLK * 4)/4
(OSCCLK * 4)/2
(OSCCLK * 4)/1
00101
(OSCCLK * 5)/4
(OSCCLK * 5)/2
(OSCCLK * 5)/1
00110
(OSCCLK * 6)/4
(OSCCLK * 6)/2
(OSCCLK * 6)/1
00111
(OSCCLK * 7)/4
(OSCCLK * 7)/2
(OSCCLK * 7)/1
01000
(OSCCLK * 8)/4
(OSCCLK * 8)/2
(OSCCLK * 8)/1
01001
(OSCCLK * 9)/4
(OSCCLK * 9)/2
(OSCCLK * 9)/1
01010
(OSCCLK * 10)/4
(OSCCLK * 10)/2
(OSCCLK * 10)/1
01011
(OSCCLK * 11)/4
(OSCCLK * 11)/2
(OSCCLK * 11)/1
01100
(OSCCLK * 12)/4
(OSCCLK * 12)/2
(OSCCLK * 12)/1
01101
(OSCCLK * 13)/4
(OSCCLK * 13)/2
(OSCCLK * 13)/1
01110
(OSCCLK * 14)/4
(OSCCLK * 14)/2
(OSCCLK * 14)/1
01111
(OSCCLK * 15)/4
(OSCCLK * 15)/2
(OSCCLK * 15)/1
10000
(OSCCLK * 16)/4
(OSCCLK * 16)/2
(OSCCLK * 16)/1
(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(2) This register is EALLOW protected. See the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical
Reference Manual (literature number SPRUH18) for more information.
(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
Table 3-17. CLKIN Divide Options
PLLSTS [DIVSEL]
0
1
2
3
CLKIN DIVIDE
/4
/4
/2
/1
Copyright © 2010–2011, Texas Instruments Incorporated
Device Overview
57
Submit Documentation Feedback
Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062