TMS320F28069_1107 Datasheet, PDF (47/172 Pages) Texas Instruments – Piccolo Microcontrollers

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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698B – NOVEMBER 2010 – REVISED JULY 2011
3.6 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-9.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 3-10.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 3-11.
Peripheral Frame 3: McBSP registers are mapped to this. See Table 3-12.
Table 3-9. Peripheral Frame 0 Registers⁽¹⁾
NAME
ADDRESS RANGE
SIZE (×16)
EALLOW PROTECTED⁽²⁾
Device Emulation Registers
0x00 0880 – 0x00 0984
261
Yes
System Power Control Registers
FLASH Registers⁽³⁾
0x00 0985 – 0x00 0987
3
Yes
0x00 0A80 – 0x00 0ADF
96
Yes
Code Security Module Registers
0x00 0AE0 – 0x00 0AEF
16
Yes
ADC registers
(0 wait read only)
0x00 0B00 – 0x00 0B0F
16
No
CPU–TIMER0/1/2 Registers
0x00 0C00 – 0x00 0C3F
64
No
PIE Registers
0x00 0CE0 – 0x00 0CFF
32
No
PIE Vector Table
0x00 0D00 – 0x00 0DFF
256
No
DMA Registers
0x00 1000 – 0x00 11FF
512
Yes
CLA Registers
0x00 1400 – 0x00 147F
128
Yes
CLA to CPU Message RAM (CPU writes ignored)
0x00 1480 – 0x00 14FF
128
NA
CPU to CLA Message RAM (CLA writes ignored)
0x00 1500 – 0x00 157F
128
NA
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Copyright © 2010–2011, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062