TMS320F28069_1107 Datasheet, PDF (105/172 Pages) Texas Instruments – Piccolo Microcontrollers

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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698B – NOVEMBER 2010 – REVISED JULY 2011
Figure 6-26 is a block diagram of the SPI in slave mode.
SPIFFENA
SPIFFTX.14
RX FIFO Registers
Receiver
Overrun Flag
SPISTS.7
SPIRXBUF
RX FIFO _0
RX FIFO _1
-----
RX FIFO _3
16
RX FIFO Interrupt
SPIRXBUF
Buffer Register
TX FIFO Registers
SPITXBUF
TX FIFO _3
-----
TX FIFO _1
TX FIFO _0
16
16
SPITXBUF
Buffer Register
SPIFFOVF
FLAG
SPIFFRX.15
TX FIFO Interrupt
SPI INT FLAG
SPISTS.6
16
SPIDAT
Data Register
SPIDAT.15 - 0
Talk
SPICTL.1
M
S
SW1
M
S
SW2
Overrun
INT ENA
SPICTL.4
RX Interrupt
Logic
TX Interrupt
Logic
SPI INT
ENA
SPICTL.0
M
S
M _TW
TW
S
SPIINT
To CPU
SPITX
TRIWIRE
SPIPRI.0
TW
STEINV
State Control
SPI Char
SPICCR.3 - 0
32 10
LSPCLK
SPI Bit Rate
SPIBRR.6 - 0
65 432 10
Master/Slave
SPICTL.2
S
SW3
M
S
M
Clock
Polarity
SPICCR.6
Clock
Phase
SPICTL.3
STEINV
SPIPRI.1
SPISIMO
SPISOMI
SPISTE
SPICLK
A. SPISTE is driven low by the master for a slave device.
Figure 6-26. SPI Module Block Diagram (Slave Mode)
6.12.1 Serial Peripheral Interface (SPI) Master Mode Electrical Data/ Timing
Table 6-29 lists the master mode timing (clock phase = 0) and Table 6-30 lists the master mode timing
(clock phase = 1). Figure 6-27 and Figure 6-28 show the timing waveforms.
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Peripheral and Electrical Specifications 105
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