TM4C1237D5PM Datasheet, PDF (561/1264 Pages) Texas Instruments – Floating-Point Status Control (FPSC)

Tiva^™ TM4C1237D5PM Microcontroller _{(identical to LM4F130C4QR)}
Table 9-1. μDMA Channel Assignments (continued)
Enc.
0
Ch # Peripheral
21 GPTimer 1B
22 UART1 RX
23 UART1 TX
24 SSI1 RX
25 SSI1 TX
26 Software
27 Software
28 Software
29 Software
30 Software
31 Reserved
1
Type Peripheral
B Software
SB Software
SB Software
SB ADC1 SS0
SB ADC1 SS1
B ADC1 SS2
B ADC1 SS3
B Software
B Software
B Software
B Reserved
2
Type Peripheral
B UART7 TX
B Software
B Software
B Software
B Software
B Software
B Software
B Software
B Software
B Software
B Reserved
3
4
Type Peripheral Type Peripheral
SB Software
B Software
B Software
B Software
B Software
B Software
B GPWideTimer 3A B Software
B GPWideTimer 3B B Software
B GPWideTimer 4A B Software
B GPWideTimer 4B B Software
B GPWideTimer 5A B Software
B GPWideTimer 5B B Software
B Software
B Software
B Reserved
B Reserved
Type
B
B
B
B
B
B
B
B
B
B
B
9.2.2
Priority
The μDMA controller assigns priority to each channel based on the channel number and the priority
level bit for the channel. Channel number 0 has the highest priority and as the channel number
increases, the priority of a channel decreases. Each channel has a priority level bit to provide two
levels of priority: default priority and high priority. If the priority level bit is set, then that channel has
higher priority than all other channels at default priority. If multiple channels are set for high priority,
then the channel number is used to determine relative priority among all the high priority channels.
The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET)
register and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register.
9.2.3
Arbitration Size
When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels
making a request and services the μDMA channel with the highest priority. Once a transfer begins,
it continues for a selectable number of transfers before rearbitrating among the requesting channels
again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers.
After the μDMA controller transfers the number of items specified by the arbitration size, it then
checks among all the channels making a request and services the channel with the highest priority.
If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels
is increased because the μDMA controller completes the lower priority burst before checking for
higher priority requests. Therefore, lower priority channels should not use a large arbitration size
for best response on high priority channels.
The arbitration size can also be thought of as a burst size. It is the maximum number of items that
are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA
channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the
processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor
must perform a bus transaction on the same bus, even in the middle of a burst transfer.
9.2.4
Request Types
The μDMA controller responds to two types of requests from a peripheral: single or burst. Each
peripheral may support either or both types of requests. A single request means that the peripheral
July 16, 2013
561
Texas Instruments-Production Data