TM4C1237D5PM Datasheet, PDF (1093/1264 Pages) Texas Instruments – Floating-Point Status Control (FPSC)

Tiva^™ TM4C1237D5PM Microcontroller _{(identical to LM4F130C4QR)}
OTG A /
Host
OTG B /
Device
15
Type RO
Reset
0
Register 4: USB Receive Interrupt Status (USBRXIS), offset 0x004
Important: This register is read-sensitive. See the register description for details.
USBRXIS is a 16-bit read-only register that indicates which of the interrupts for receive endpoints
1–7 are currently active.
Note: Bits relating to endpoints that have not been configured always return 0. Note also that all
active interrupts are cleared when this register is read.
USB Receive Interrupt Status (USBRXIS)
Base 0x4005.0000
Offset 0x004
Type RO, reset 0x0000
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
EP7
EP6
EP5
EP4
EP3
EP2
EP1 reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
15:8
7
Name
reserved
EP7
Type
RO
RO
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RX Endpoint 7 Interrupt
Value Description
0 No interrupt.
1 The Endpoint 7 transmit interrupt is asserted.
6
EP6
RO
0
RX Endpoint 6 Interrupt
Same description as EP7.
5
EP5
RO
0
RX Endpoint 5 Interrupt
Same description as EP7.
4
EP4
RO
0
RX Endpoint 4 Interrupt
Same description as EP7.
3
EP3
RO
0
RX Endpoint 3 Interrupt
Same description as EP7.
2
EP2
RO
0
RX Endpoint 2 Interrupt
Same description as EP7
1
EP1
RO
0
RX Endpoint 1 Interrupt
Same description as EP7.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 16, 2013
Texas Instruments-Production Data
1093