TM4C1237D5PM Datasheet, PDF (466/1264 Pages) Texas Instruments – Floating-Point Status Control (FPSC)

System Exception Module
Bit/Field
2
1
0
Name
FPIOCMIS
FPDZCMIS
FPIDCMIS
Type
RO
RO
RO
Reset
0
0
0
Description
Floating-Point Invalid Operation Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an invalid operation.
This bit is cleared by writing a 1 to the FPIOCIC bit in the SYSEXCIC
register.
Floating-Point Divide By 0 Exception Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a divide by 0
exception.
This bit is cleared by writing a 1 to the FPDZCIC bit in the SYSEXCIC
register.
Floating-Point Input Denormal Exception Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an input denormal
exception.
This bit is cleared by writing a 1 to the FPIDCIC bit in the SYSEXCIC
register.
466
July 16, 2013
Texas Instruments-Production Data