TMS570LS1227 Datasheet, PDF (56/184 Pages) Texas Instruments – TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller

TMS570LS1227
SPNS192B – OCTOBER 2012 – REVISED FEBRUARY 2015
www.ti.com
6.3 Power Sequencing and Power On Reset
6.3.1 Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-
up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for
more details), core voltage rising above the minimum core supply threshold and the release of power-on
reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The
oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The
different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 6-3. Power-Up Phases
Oscillator start-up and validity check
eFuse autoload
Flash pump power-up
Flash bank power-up
Total
1032 oscillator cycles
1160 oscillator cycles
688 oscillator cycles
617 oscillator cycles
3497 oscillator cycles
The CPU reset is released at the end of the above sequence and fetches the first instruction from address
0x00000000.
6.3.2 Power-Down Sequence
The different supplies to the device can be powered down in any order.
6.3.3 Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
6.3.3.1 nPORRST Electrical and Timing Requirements
NO Parameter
V_CCPORL
V_CCPORH
V_CCIOPORL
V_CCIOPORH
V_IL(PORRST)
3 t_su(PORRST)
6 t_h(PORRST)
7 t_su(PORRST)
8 t_h(PORRST)
9 t_h(PORRST)
Table 6-4. Electrical Requirements for nPORRST
V_CC low supply level when nPORRST must be active during power-
up
V_CC high supply level when nPORRST must remain active during
power-up and become active during power down
V_CCIO / V_CCP low supply level when nPORRST must be active during
power-up
V_CCIO / V_CCP high supply level when nPORRST must remain active
during power-up and become active during power down
Low-level input voltage of nPORRST V_CCIO > 2.5V
Low-level input voltage of nPORRST V_CCIO < 2.5V
Setup time, nPORRST active before V_CCIO and V_CCP > V_CCIOPORL
during power-up
Hold time, nPORRST active after V_CC > V_CCPORH
Setup time, nPORRST active before V_CC < V_CCPORH during power
down
Hold time, nPORRST active after V_CCIO and V_CCP > V_CCIOPORH
Hold time, nPORRST active after V_CC < V_CCPORL
MIN
1.14
3.0
0
1
2
1
0
MAX
0.5
1.1
0.2 * V_CCIO
0.5
Unit
V
V
V
V
V
V
ms
ms
µs
ms
ms
56
System Information and Electrical Specifications
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