TLC320AD75 Datasheet, PDF (5/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

List of Illustrations
Figure
Title
Page
Figure 2–1 ADC Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Figure 2–2 DAC-Reset Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Figure 2–3 Differential Analog-Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Figure 2–4 ADC Audio-Data Serial Timing – Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Figure 2–5 ADC Audio-Data Serial Timing – Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Figure 2–6 Audio Data Serial Timing – ADC and All DAC Modes . . . . . . . . . . . . . . . . . . . . . 2–6
Figure 2–7 Control-Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Figure 2–8 De-emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Figure 2–9 Digital Attenuation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Figure 2–10 DAC Digital Attenuation Operation With Tapered Gain Response . . . . . . . . . 2–8
Figure 2–11 Oversampling Noise Power With and Without Noise Shaping . . . . . . . . . . . . . 2–9
Figure 4–1 ADC Audio-Data Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Figure 4–2 DAC Control-Data Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Figure 5–1 TLC320AD75C Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Figure 5–2 A-Weighted Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Figure 5–3 Land Pattern for PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
List of Tables
Table
Title
Page
Table 2–1 ADC Master Clock to Sample-Rate Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Table 2–2 DAC Master Clock to Sample-Rate Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Table 2–3 Attenuation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
Table 2–4 System Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Table 5–1 TLC320AD75C Schematic Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Table 5–2 A-Weighted Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
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