TLC320AD75 Datasheet, PDF (11/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

1.6 Terminal Functions
TERMINAL
NAME
NO.
ADOUT
12
APD
6
AVDD
4
AVSS
5
AVSSB
51
CDIN
19
DDATA
27
DPD
16
INIT
18
INLM
55
INLP
56
INRM
2
INRP
1
LATCH
21
LRCKA
10
LRCKD
28
LVDD
52
LVSS
53
L1
41
L2
39
MCLKI
15
I/O
DESCRIPTION
20-bit ADC data output. ADOUT provides the MSB first in 2’s-complement data format
O and is left justified within the 32-bit packet for each channel. The output level is 3.3 V
for V35A = 3.3 V (see Figure 2–6).
Analog power-down mode. APD disables the ADC analog modulators. The ADC
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single-bit modulator outputs become invalid, rendering the outputs of the digital filters
invalid. When APD is pulled high, normal operation of the device is resumed.
Analog power supply voltage for ADC modulators
Analog ground for ADC modulators
Analog substrate ground for ADC modulators
Attenuation mode and system control mode input for DAC. CDIN is a 24-bit stream
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with a 16-bit data word followed by an 8-bit device address. This stream is configured
with the MSB first (see Section 2.15, Sigma-Delta DAC Modulator).
DAC input data in 2’s-complement data format. MSB/LSB first and 20-bit/16-bit input
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formats are selectable by using the DAC control registers (see Section 2.15,
Sigma-Delta DAC Modulator).
Digital power-down mode. The DPD shuts down the ADC digital decimation filters and
clock generators, and provides a digital reset. All digital outputs of the ADC function,
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are brought to unasserted states. When DPD is pulled high, normal operation of the
device is resumed. When in slave mode operation, after the rising edge of DPD, the
ADC system is synchronized.
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Initial DAC reset signal. The DAC device is activated on the rising edge of INIT. When
INIT is brought low, the DAC is reset when LRCKD is present.
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Inverting input for the left channel analog modulator
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Noninverting input for the left channel analog modulator
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Inverting input for the right channel analog modulator
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Noninverting input for the right channel analog modulator
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Latch signal for the DAC control serial data. Attenuation/system-control data loads
into the internal registers when LATCH is brought low.
Left/right clock for ADC. LRCKA signifies whether the serial data is associated with
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the left channel ADC (when LRCKA is high) or the right channel ADC (when LRCKA
is low). LRCKA is normally connected to LRCKD. LRCKA is output when configured
in master mode.
Left/right clock for DAC. LRCKD signifies whether the serial data is associated with
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the left channel DAC (when LRCKD is high) or the right channel DAC (when LRCKD
is low). LRCKD is normally connected to LRCKA.
Digital power supply for analog modulators. LVDD is normally connected to AVDD
through a 50-Ω resistor.
Digital ground for analog modulators. LVSS is normally connected to AVSS through a
50-Ω resistor.
O Left channel DAC PWM output 1
O Left channel DAC PWM output 2
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Master clock input for ADC. MCLKI operates at 256 times the sample rate (i.e. 256
times LRCKA). MCLKI is normally connected to 256CK through a 50-Ω resistor.
1–5