TLC320AD75 Datasheet, PDF (19/43 Pages) Texas Instruments – 20-Bit Sigma-Delta Stereo ADA Circuit

2.11 Serial-Control Interface for DAC
The TLC320AD75C uses the most-significant-bit-first format. Therefore, for a 16-bit data word, D16 is the
most significant bit (MSB) and D1 is the least significant bit (LSB).
2.11.1 Serial-Control-Data Input
The 16-bit control-data input implements the device-control functions. The TLC320AD75C has two registers
for this data: the system register and the attenuation register. The system register contains most of the
system configuration information, and the attenuation register controls the audio output level and
deemphasis. Figure 2–7 illustrates the input timing for CDIN, SHIFT, and LATCH. The data loads internally
during the low level of LATCH. The shift clock must be high or low for the LATCH setup time before LATCH
goes low.
As shown in Figure 2–7, CDIN is a 24-bit data stream consisting of 16 bits of control data D16 through D1
followed by 8 bits of device, address A8 through A1. When the TLC320AD75C receives address >E7h, the
control data is latched into the device by LATCH. For all other addresses, the data is ignored.
Control Data
Control-Device Address
CDIN
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 A8 A7 A6 A5 A4 A3 A2 A1
SHIFT
LATCH
Figure 2–7. Control-Data Input Timing
2.12 DAC De-emphasis Filter
Three sets of de-emphasis-filter coefficients support the three sampling rates (f_s): 32 kHz, 44.1 kHz, and
48 kHz. Internal system-register values select the filter coefficients. The internal register values enable or
disable the filter. Figure 2–8 illustrates the de-emphasis filtering characteristics.
Many audio sources have been recorded with pre-emphasis characteristics that are the inverse of the
characteristics shown in Figure 2–8. This device provides reconstruction of the original frequency response.
10
0
De-emphasis
– 10
3.18
(50 µs)
f – Frequency – kHz
10.6
(15 µs)
Figure 2–8. De-emphasis Filter Characteristics
2.13 Digital Filter Mute for DAC
When the mute bit in the attenuation register is set to 1, the DAC digital filter mute is active. The output of
the digital filter is 0 + dc offset. Operation of the digital filter is normal during mute.
2–7