LMK00301 Datasheet, PDF (5/26 Pages) Texas Instruments – 3-GHz, 10-Output Differential Fanout Buffer / Level Translator

7.0 Functional Description
The LMK00301 is a 10 output differential clock fanout buffer
with low additive jitter that can operate up to 3.1 GHz. It fea-
tures a 3:1 input multiplexer with a crystal oscillator input, two
banks of 5 differential outputs with multi-mode buffers
(LVPECL, LVDS, HCSL, or Hi-Z) , one LVCMOS output, sin-
gle supply or dual supply (lower power) operation, and pin-
controlled device configuration. The device is offered in a 48-
pin LLP package and leverages much of the high-speed, low-
noise circuit design employed in the LMK04800 family of clock
conditioners.
7.1 V_CC and V_CCO Power Supplies
Separate Vcc core and Vcco output supplies allow the output
buffers to operate the same voltage as the 3.3 V core supply
or from a lower 2.5 V supply. Compared to single-supply op-
eration, dual 3.3 V/2.5 V supply operation enables lower
power consumption and output-level compatibility with 2.5 V
receiver devices. The output levels for LVPECL (V_OH, V_OL)
and LVCMOS (V_OH) are referenced to the Vcco supply, while
the output levels for LVDS and HCSL are relatively constant
over the specified Vcco range. Refer to Section 14.4 Power
Supply and Thermal Considerations for additional supply re-
lated considerations, such as power dissipation, power sup-
ply bypassing, and power supply ripple rejection (PSRR).
Note: Care should be taken to ensure the Vcco voltage does not exceed
the Vcc voltage to prevent turning-on the internal ESD protection cir-
cuitry.
7.2 Clock Inputs
The input clock can be selected from CLKin0/CLKin0*,
CLKin1/CLKin1*, or OSCin. Clock input selection is controlled
using the CLKin_SEL[1:0] inputs as shown in Table 1. Refer
to Section 14.1 Driving the Clock Inputs for clock input re-
quirements. When CLKin0 or CLKin1 is selected, the crystal
circuit is powered down. When OSCin is selected, the crystal
oscillator circuit will start-up and its clock will be distributed to
all outputs. Refer to Section 14.2 Crystal Interface for more
information. Alternatively, OSCin may be be driven by a sin-
gle-ended clock (up to 250 MHz) instead of a crystal.
TABLE 1. Input Selection
CLKin_SEL1 CLKin_SEL0
Selected Input
0
0
CLKin0, CLKin0*
0
1
CLKin1, CLKin1*
1
X
OSCin
Table 2 shows the output logic state vs. input state when ei-
ther CLKin0/CLKin0* or CLKin1/CLKin1* is selected. When
OSCin is selected, the output state will be an inverted copy of
the OSCin input state.
TABLE 2. CLKin Input vs. Output States
State of
Selected CLKin
State of
Enabled Outputs
CLKinX and CLKinX*
inputs floating
Logic low
CLKinX and CLKinX*
inputs shorted together
Logic low
CLKin logic low
Logic low
CLKin logic high
Logic high
7.3 Clock Outputs
The differential output buffer type for Bank A and Bank B out-
puts can be separately configured using the CLKoutA_TYPE
[1:0] and CLKoutB_TYPE[1:0] inputs, respectively, as shown
in Table 3. If an entire output bank will not be used, it is rec-
ommended to disable the bank to reduce power. Refer to
Section 14.3 Termination and Use of Clock Drivers for more
information on output interface and termination techniques.
TABLE 3. Differential Output Buffer Type Selection
CLKoutX_ CLKoutX_
TYPE1
TYPE0
CLKoutX Buffer Type
(Bank A or B)
0
0
LVPECL
0
1
LVDS
1
0
HCSL
1
1
Disabled (Hi-Z)
7.3.1 Reference Output
The reference output (REFout) provides a LVCMOS copy of
the selected input clock. The LVCMOS output high level is
referenced to the Vcco voltage. REFout can be enabled or
disabled using the enable input pin, REFout_EN, as shown in
Table 4.
TABLE 4. Reference Output Enable
REFout_EN
REFout State
0
Disabled (Hi-Z)
1
Enabled
The REFout_EN input is internally synchronized with the se-
lected input clock by the SYNC block. This synchronizing
function prevents glitches and runt pulses from occurring on
the REFout clock when enabled or disabled. REFout will be
enabled within 3 cycles (t_EN) of the input clock after
REFout_EN is toggled high. REFout will be disabled within 3
cycles (t_DIS) of the input clock after REFout_EN is toggled low.
When REFout is disabled, the use of a resistive loading can
be used to set the output to a predetermined level. For ex-
ample, if REFout is configured with a 1 kΩ load to ground,
then the output will be pulled to low when disabled.
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