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LMK00301 Datasheet, PDF (10/26 Pages) Texas Instruments – 3-GHz, 10-Output Differential Fanout Buffer / Level Translator
Symbol
Parameter
Conditions
Min Typ Max
HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout
Output Frequency Range
(Note 15)
RL = 50 Ω to GND, CL ≤ 5 pF
DC
400
JitterADD
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz
(Note 12)
Vcco = 3.3 V,
RT = 50 Ω to GND
CLKin: 100 MHz, Slew
rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
77
86
Noise Floor
Noise Floor
fOFFSET ≥ 10 MHz
Vcco = 3.3 V,
RT = 50 Ω to GND
CLKin: 100 MHz, Slew
rate ≥ 3 V/ns
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns
-161.3
-156.3
DUTY
Duty Cycle (Note 15)
50% input clock duty cycle
45
55
VOH
VOL
VCROSS
ΔVCROSS
Output High Voltage
Output Low Voltage
Absolute Crossing Voltage
(Note 15, Note 17)
Total Variation of VCROSS
(Note 15, Note 17)
TA = 25 °C, DC Measurement,
RT = 50 Ω to GND
RL = 50 Ω to GND,
CL ≤ 5 pF
520
810
920
-150
0.5
150
160
350
460
140
tR
Output Rise Time
20% to 80% (Note 17)
250 MHz, RL = 50 Ω to GND,
300
tF
Output Fall Time
80% to 20% (Note 17)
CL ≤ 5 pF
300
LVCMOS Output (REFout)
fCLKout
Output Frequency Range
(Note 15)
CL ≤ 5 pF
DC
250
Additive RMS Jitter
JitterADD
Integration Bandwidth
1 MHz to 20 MHz
Vcco = 3.3 V,
CL ≤ 5 pF
100 MHz, Input Slew
rate ≥ 3 V/ns
95
(Note 12)
Noise Floor
DUTY
Noise Floor
fOFFSET ≥ 10 MHz
Duty Cycle (Note 15)
Vcco = 3.3 V,
CL ≤ 5 pF
100 MHz, Input Slew
rate ≥ 3 V/ns
-159.3
50% input clock duty cycle
45
55
VOH
Output High Voltage
1 mA load
Vcco –
0.1
VOL
Output Low Voltage
IOH
Output High Current (Source)
Vo = Vcco / 2
IOL
Output Low Current (Sink)
Vcco = 3.3 V
Vcco = 2.5 V
Vcco = 3.3 V
Vcco = 2.5 V
0.1
28
20
28
20
tR
Output Rise Time
20% to 80% (Note 17)
250 MHz, RL = 50 Ω to GND,
225
tF
Output Fall Time
80% to 20% (Note 17)
CL ≤ 5 pF
225
tEN
Output Enable Time (Note 18)
tDIS
Output Disable Time (Note 18)
CL ≤ 5 pF
3
3
Units
MHz
fs
dBc/Hz
%
mV
mV
mV
mV
ps
ps
MHz
fs
dBc/Hz
%
V
V
mA
mA
ps
ps
cycles
cycles
9
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