LMK00301 Datasheet, PDF (2/26 Pages) Texas Instruments – 3-GHz, 10-Output Differential Fanout Buffer / Level Translator

LMK00301
November 1, 2011
3-GHz, 10-Output Differential Fanout Buffer / Level
Translator
1.0 General Description
The LMK00301 is a 3-GHz, 10-output differential fanout buffer
intended for high-frequency, low-jitter clock/data distribution
and level translation. The input clock can be selected from
two differential inputs or one crystal input. The selected input
clock is distributed to two banks of 5 differential outputs and
one LVCMOS output. Each output bank can be configured as
LVPECL, LVDS, or HCSL drivers, or disabled to reduce pow-
er. The LVCMOS output has a synchronous enable input for
runt-pulse-free operation when enabled or disabled. The
LMK00301 can be powered from a single 3.3 V supply, or dual
3.3 V/2.5 V supplies for lower power operation.
The LMK00301 provides high performance, versatility, and
power efficiency, making it ideal for replacing fixed-output
buffer devices while increasing timing margin in the system.
2.0 Target Applications
■ ^{Clock Distribution and Level Translation for high-speed}
ADCs, DACs, and Serial Interfaces (Multi-Gigabit
Ethernet, XAUI, Fibre Channel, PCIe, SATA/SAS,
SONET/SDH, CPRI)
■ ^{Remote Radio Units (RRU) and Baseband Units (BBU)}
■ ^{Switches and Routers}
■ ^{Servers, Workstations, and Computing}
■ ^{High Frequency Backplanes}
3.0 Features
■ ^{3:1 Input Multiplexer}
— Two differential inputs accept DC-coupled LVPECL,
LVDS, CML, SSTL, HSTL and single-ended clocks
— Differential input operates from DC to 3.1 GHz
— One crystal input accepts a 10 to 40 MHz crystal or
single-ended clock
■ ^{Two Banks with 5 Differential Outputs each}
— Selectable output type (per bank): LVPECL, LVDS,
HCSL, or Hi-Z
— 51 fs RMS Additive Jitter for LVPECL at 156.25 MHz
(12 kHz – 20 MHz) with LMK03806 clock source
■ ^{LVCMOS output with synchronous enable input}
■ ^{Pin-controlled configuration}
■ ^{Core Supply: 3.3 V ± 5%, Output Supply: 3.3 V/2.5 V ± 5%}
■ ^{Industrial temperature range: -40°C to +85°C}
■ ^{Package: 48-pin LLP (7.0 x 7.0 x 0.8 mm)}
4.0 Functional Block Diagram
© 2011 Texas Instruments Incorporated 301470
30147001
www.ti.com