LMK00301 Datasheet, PDF (11/26 Pages) Texas Instruments – 3-GHz, 10-Output Differential Fanout Buffer / Level Translator

Symbol
t_{PD_PECL}
t_{PD_LVDS}
t_{PD_HCSL}
t_{PD_CMOS}
t_SK(O)
t_SK(PP)
Parameter
Conditions
Min
Propagation Delay and Output Skew
Propagation Delay
CLKin-to-LVPECL
Propagation Delay
CLKin-to-LVDS
R_T = 160 Ω to GND,
R_L = 100 Ω differential
R_L = 100 Ω differential
Propagation Delay
CLKin-to-HCSL (Note 17)
Propagation Delay
CLKin-to-LVCMOS (Note 17)
R_T = 50 Ω to GND,
C_L ≤ 5 pF
C_L ≤ 5 pF
Vcco = 3.3 V
Vcco = 2.5 V
Output Skew
LVPECL/LVDS/HCSL
(Note 15, Note 17, Note 19)
Part-to-Part Output Skew
LVPECL/LVDS/HCSL
(Note 17, Note 19)
Skew specified between any two CLKouts
with the same buffer type. Load conditions
per output type are the same as propagation
delay specifications.
Typ Max
360
400
590
1475
1550
30
50
80
Units
ps
ps
ps
ps ps
ps
ps
Note 7: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 8: See Section 14.4 Power Supply and Thermal Considerations for more information on current consumption and power dissipation calculations.
Note 9: Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone
sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic
π jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 * 10^{(PSRR / 20)}) / ( * f^CLK) ] * 1E12
Note 10: See Section 12.1 Differential Voltage Measurement Terminology for definition of V_ID and V_OD voltages.
Note 11: The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may
be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Section 14.2 Crystal Interface for crystal drive level
considerations.
Note 12: For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (J_ADD) is calculated using Method #1: J_ADD = SQRT(J_OUT2 – J_SOURCE2),
π ^{where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625 MHz clock input}
condition, Additive RMS Jitter is approximated using Method #2: J_ADD = SQRT(2*10^dBc/10) / (2* *f_CLK), where dBc is the phase noise power of the Output Noise
Floor integrated from 1 to 20 MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10*log₁₀(20 MHz – 1 MHz). The additive RMS
jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method
#1. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Section 13.0 Typical Performance Characteristics.
Note 13: The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this
measurement offset can be as low as 5 MHz due to measurement equipment limitations.
Note 14: Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS)
will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest
possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.
Note 15: Specification is guaranteed by characterization and is not tested in production.
Note 16: See Section 13.0 Typical Performance Characteristics for output operation over frequency.
Note 17: AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.
Note 18: Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable
Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition
much faster than that of the input clock period for accurate measurement.
Note 19: Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same
supply voltage and temperature conditions.
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