DS64MB201 Datasheet, PDF (5/28 Pages) Texas Instruments – DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

Pin Name
Pin Number I/O, Type Pin Description
Control Pins — Both Modes (LVCMOS)
RATE
21
I, Float,
RATE, 3–level input controls the pulse width of de-emphasis of the output.
LVCMOS RATE = 0 forces ~3 Gbps,
RATE = 1 forces ~6 Gbps,
RATE = Float enables auto rate detection. See Table 2
TXIDLEDO
24
I, Float,
LVCMOS
TXIDLEDO, 3–level input controls the driver output.
TXIDLEDO = 0 disables the signal detect/squelch function for DOUT.
TXIDLEDO = 1 forces the DOUT to be muted (electrical idle).
TXIDLEDO = Float enables the signal auto detect/squelch function for DOUT
and the signal detect voltage threshold level can be adjusted using the
SD_TH pin. See Table 3
TXIDLESO
25
I, Float,
LVCMOS
TXIDLESO, 3–level input controls the driver output.
TXIDLESO = 0 disables the signal detect/squelch function for SOUT.
TXIDLESO = 1 forces the SOUT to be muted (electrical idle).
TXIDLESO = Float enables the signal auto detect/squelch function for SOUT
and the signal detect voltage threshold level can be adjusted using the
SD_TH pin. See Table 3
FANOUT
26
I, LVCMOS w/ FANOUT = 1 enables both A/B outputs for broadcast mode.
internal pull- FANOUT = 0 disables one of the outputs depending on the SEL0, SEL1 pin.
down
See Table 5
SEL0, SEL1
19, 20
I, LVCMOS w/ SEL0 is for lane 0, SEL1 is for lane 1
internal pull- SEL0, SEL1 = 0 selects B input and B output.
down
SEL0, SEL1 = 1 selects A input and A output. See Table 5
VOD0, VOD1
22, 23
I, LVCMOS w/ VOD[1:0] adjusts the output differential amplitude voltage level on all outputs.
internal pull- 00 set output VOD = 600 mVp-p (Default)
down
01 sets output VOD = 800 mVp-p
10 sets output VOD = 1000 mVp-p
11 sets output VOD = 1200 mVp-p
Note: VOD should be set to a minimum of 1000 mV to achieve stated DE
levels.
Analog
SD_TH
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for default
130 mVp-p (differential).
See Table 4
Power
VDD
9, 14, 36, 41, Power
51
2.5V Power supply pins.
GND
DAP, 52
Power
DAP is the large metal contact at the bottom side, located at the center of the
54 pin LLP package. It should be connected to the GND plane with at least 4
via to lower the ground impedance and improve the thermal performance of
the package.
NOTE: DAP is the primary GND
NC
1, 2, 5, 6, 12,
13, 17, 18
No Connect — Leave pin open
1 = HIGH, 0 = LOW, FLOAT = 3rd input state.
FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pull-up/pull-down.
Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
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