DS64MB201 Datasheet, PDF (14/28 Pages) Texas Instruments – DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

System Management Bus (SMBus)
and Configuration Registers
The System Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification. ENSMB must be pulled
high to enable SMBus mode and allow access to the config-
uration registers.
The DS64MB201 has the AD[3:0] inputs in SMBus mode.
These pins set the SMBus slave address inputs. The AD[3:0]
pins have internal pull-down. When left floating or pulled low
the AD[3:0] = 0000'b, the device default address byte is A0'h.
Based on the SMBus 2.0 specification, the DS64MB201 has
a 7-bit slave address of 1010000'b. The LSB is set to 0'b (for
a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The
bold bits indicate the AD[3:0] pin map to the slave address
bits [4:1]. The device address byte can be set with the use of
the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDC and SDA pins are 3.3V LVCMOS signaling and in-
clude high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon
SMBus loading and speed. Note, these pins are not 5V tol-
erant.
TRANSFER OF DATA VIA THE SMBUS
During normal operation the data on SDA must be stable dur-
ing the time when SDC is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SDC is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High
indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding
t_BUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for t_HIGH then
the bus will transfer to the IDLE state.
SMBUS TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
When SMBus is enabled, all outputs of the DS64MB201 must
use one of the following De-emphasis settings (Table 6).
The driver de-emphasis value is set on a per lane basis using
6 different registers. Each register (0x18, 0x26, 0x2E, 0x35,
0x3C, 0x43) requires one of the following De-emphasis set-
tings when in SMBus mode. The VOD for each output should
be set via register write or pin control to be a minimum of 1000
mV.
TABLE 6. De-Emphasis Register Settings (must write one of the following when in SMBus mode)
De-Emphasis Value
0.0 dB
-3.5 dB
-6 dB
-9 dB
-12 dB
Register Setting
0x01
0xE8
0x88
0x90
0xA0
3 Gbps Operation
6 Gbps Operation
10” trace or 1 meter 28 awg cable 5” trace or 0.5 meter 28 awg cable
20” trace or 2 meters 28 awg cable 10” trace or 1meters 28 awg cable
25” trace or 3 meters cable
20” trace or 2 meters cable
5 meters 28 awg cable
3 meters 28 awg cable
8 meters 28 awg cable
5 meters 28 awg cable
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
RECOMMENDED SMBUS REGISTER SETTINGS
When SMBus mode is enabled (ENSMB = 1), the default reg-
ister settings are not configured to an appropriate level. Below
is the recommended settings to configure the EQ, VOD and
DE to a medium level that supports interconnect length of 20
inches FR4 trace or 3 to 5 meters of cable length. Please refer
to Table 1, Table 2, Table 6, Table 7for additional information
and recommended settings.
1. Reset the SMBus registers to default values:
Write 01'h to 0x00.
2. Set de-emphasis to -6 dB for all lanes:
Write 88'h to 0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43.
3. Set equalization to external pin level EQ[1:0] = 00 (~9 dB
at 3 GHz) for all lanes:
Write 30'h to 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x3A.
4. Set VOD = 1.0 Vp-p for all lanes:
Write 0F'h to 0x17, 0x25, 0x2D, 0x34, 0x3B, 0x42.
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