DS64MB201 Datasheet, PDF (15/28 Pages) Texas Instruments – DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

TABLE 7. SMBus Register Map
Address Register Name
0x00
Reset
0x01
PWDN lanes
Bit (s) Field
7:1 Reserved
0
Reset
7:0 PWDN CHx
0x02
PWDN Control
0x03
SEL / FANOUT
Control
7:1 Reserved
0
PWDN Control
7:3 Reserved
2
SEL1
1
SEL0
0
FANOUT
0x08
Pin Control Override 7:5
4
Reserved
Override IDLE
3
Reserved
2
Override RATE
1
Override SEL
0
Override
FANOUT
Type
R/W
R/W
R/W
R/W
R/W
Default
0x00
0x00
0x00
0x00
0x00
Description
Set bits to 0.
SMBus Reset
1: Reset registers to default value
Power Down per lane
[7]: NC — SOB1
[6]: DIN1 — SOA1
[5]: NC — SOB0
[4]: DIN0 — SOA0
[3]: SIB1 — DOUT1
[2]: SIA1 — NC
[1]: SIB0 — DOUT0
[0]: SIA0 — NC
00'h = all lanes enabled
FF'h = all lanes disabled
Set bits to 0.
0: Normal operation
1: Enable PWDN control in Register 0x01
Set bits to 0.
0: Selects SIB1 input and SOB1 output
1: Selects SIA1 input and SOA1 output
0: Selects SIB0 input and SOB0 output
1: Selects SIA0 input and SOA0 output
0: Enable only A or B output depends on SEL1 and
SEL0 (See Mux Control Truth Table)
1: Enable both SOAn and SOBn output
Set bits to 0.
0: Allow IDLE pin control
1: Block IDLE pin control
Set bit to 0.
0: Allow RATE pin control
1: Block RATE pin control
0: Allow SEL pin control
1: Block SEL pin control
0: Allow FANOUT pin control
1: Block FANOUT pin control
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