DS64MB201 Datasheet, PDF(24/28 Page) Texas Instruments – DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

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DS64MB201 Datasheet, PDF (24/28 Pages) Texas Instruments – DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

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Applications Information

GENERAL RECOMMENDATIONS

The DS64MB201 is a high performance circuit capable of de-

livering excellent performance. Careful attention must be paid

to the details associated with high-speed design as well as

providing a clean power supply. Refer to the LVDS Owner's

Manual for more detailed information on high speed design

tips to address signal integrity design issues.

PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL

PAIRS

The CML inputs and LPDS outputs must have a controlled

differential impedance of 100â¦. It is preferable to route dif-

ferential lines exclusively on one layer of the board, particu-

larly for the input traces. The use of vias should be avoided if

possible. If vias must be used, they should be used sparingly

and must be placed symmetrically for each side of a given

differential pair. Route the differential signals away from other

signals and noise sources on the printed circuit board. See

AN-1187 for additional information on LLP packages.

POWER SUPPLY BYPASSING

Two approaches are recommended to ensure that the

DS64MB201 is provided with an adequate power supply.

First, the supply (VDD) and ground (GND) pins should be

connected to power planes routed on adjacent layers of the

printed circuit board. The layer thickness of the dielectric

should be minimized so that the VDD and GND planes create

a low inductance supply with distributed capacitance. Sec-

ond, careful attention to supply bypassing through the proper

use of bypass capacitors is required. A 0.01 Î¼F bypass ca-

pacitor should be connected to each VDD pin such that the

capacitor is placed as close as possible to the DS64MB201.

Smaller body size capacitors can help facilitate proper com-

ponent placement. Additionally, three capacitors with capac-

itance in the range of 2.2 Î¼F to 10 Î¼F should be incorporated

in the power supply bypassing design as well. These capac-

itors can be either tantalum or an ultra-low ESR ceramic.

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