DS64MB201 Datasheet, PDF (4/28 Pages) Texas Instruments – DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

Pin Descriptions
Pin Name
Pin Number I/O, Type Pin Description
Differential High Speed I/O's
SIA0+, SIA0-,
SIA1+, SIA1-
45, 44,
40, 39
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD
when enabled.
SOA0+, SOA0-, 35, 34,
O
SOA1+, SOA1- 31, 30
Inverting and non-inverting low power differential signaling 50Ω outputs with
de-emphasis. Fully compatible with AC coupled CML inputs.
SIB0+, SIB0-,
SIB1+, SIB1-
43, 42,
38, 37
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
SOB0+, SOB0-, 33, 32,
O
SOB1+, SOB1- 29, 28
Inverting and non-inverting low power differential signaling 50Ω outputs with
de-emphasis. Fully compatible with AC coupled CML inputs.
DIN0+, DIN0-,
DIN1+, DIN1-
10, 11,
15, 16
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated
on-chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
DOUT0+, DOUT0-, 3, 4,
O
DOUT1+, DOUT1- 7, 8
Inverting and non-inverting low power differential signaling 50Ω outputs with
de-emphasis. Fully compatible with AC coupled CML inputs.
Control Pins — Shared (LVCMOS)
ENSMB
48
I, LVCMOS w/ System Management Bus (SMBus) enable pin.
internal pull- HIGH = Register Access: Provides access to internal digital registers to
down
control such functions as equalization, de-emphasis, VOD, rate, channel
powerdown, and idle detection threshold.
LOW = Pin Mode: Access to the SMBus registers are disabled and control
pins are used to program VOD, rate, idle detection, equalization and de-
emphasis settings.
Please refer to “SMBus configuration Registers” section and Electrical
Characteristics - Serial Management Bus Interface for detailed information.
ENSMB = 1 (SMBUS MODE)
SDA, SCL
49, 50
I, LVCMOS
ENSMB = 1
The SMBus SDA (data input/output bi-directional) and SCL (clock input) pins
are enabled.
AD[3:0]
54, 53, 47, 46 I, LVCMOS w/ ENSMB = 1
internal pull- SMBus Slave Address Inputs. In SMBus mode, these pins are the user set
down
SMBus slave address inputs.
ENSMB = 0 (NORMAL PIN MODE)
EQA,
EQB,
EQD
46,
I, Float,
EQA/B/D, 3–level input controls the level of equalization.
49,
LVCMOS EQA controls the level of equalization of the SIA0 and SIA1 inputs.
53
EQB controls the level of equalization of the SIB0 and SIB1 inputs.
EQD controls the level of equalization of the DIN0 and DIN1 inputs.
The pins are active only when ENSMB is de-asserted (Low).
When ENSMB goes high the SMBus control registers provide independent
control of each lane. See Table 1
DEMA,
47,
I, Float,
DEMA/B/D, 3–level input controls the level of de-emphasis.
DEMB,
50,
LVCMOS DEMA controls the level of de-emphasis of the SOA0 and SOA1 outputs.
DEMD
54
DEMB controls the level of de-emphasis of the SOB0 and SOB1 outputs.
DEMD controls the level of de-emphasis of the DOUT0 and DOUT1 outputs.
The pins are active only when ENSMB is de-asserted (Low).
When ENSMB goes High the SMBus control registers provide independent
control of each lane. See Table 2
3
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